Memory array designers have found it advantageous to incorporate PFET MUXes (PMUXes) between precharge equalization circuits and sense amplifiers on bitlines of NFET memory arrays in order to raise the voltage of the bitline low level above ground voltage level. Raising the bitline low voltage level places the NFET access transistors of the memory array deeper into the cutoff region below the threshold voltage, which in turn reduces subthreshold leakage currents and advantageously affects the retention time of the memory array.
However, the incorporation of PMUXes in this manner has not uniformly resulted in increased memory retention time. Nonselected bitlines assume floating voltage levels during sensing intervals. Such floating voltage levels are subject to downward shifts during sensing intervals due to capacitive coupling of signals from adjacent selected bitlines. Because of such lowering of the bitline low voltage level, the subthreshold leakage current for access transistors of cells served by that bitline increases by orders of magnitude, seriously affecting the retention time for data stored in those cells. Considering that the PMUX cannot restore the voltage level on such bitlines to the desirable above ground voltage level, this coupling effect is understood to be a serious problem. Moreover, existing precharge and equalization circuits do not address this problem.
In the description below, reference is made to the drawings herein, the description of which is as follows: